Semiconductor integrated circuit having an oblique global signal wiring and semiconductor integrated circuit wiring method

ABSTRACT

A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Applications No. P2003-011631, filed onJan. 20, 2003; the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integratedcircuit and the fabrication method, particularly to the semiconductorintegrated circuit that comprises a function block and a global signalwiring, and the fabrication method.

[0004] 2. Description of the Related Art

[0005] The following design techniques are generalized for high-speed,large scale integrated circuit (LSI) design. To begin with, a circuitemployed in a semiconductor integrated circuit is converted into hardmacro blocks (function blocks) each corresponding to a function. Thefunction blocks are then automatically arranged upon the semiconductorintegrated circuit substrate, and the terminals of each function blockare electrically connected to other circuits through wiring. This typeof design is executed using a computer aided design (CAD) system.

[0006] Here, the semiconductor integrated circuit includes at least anintegrated circuit that employs standard cell method and an applicationspecific integrated circuit (ASIC) or the like. A wire herein means asignal wiring having a relatively long length passing across the entiresubstrate, such as a data bus through which transmission/reception of adata signal is performed between function blocks or with anothercircuit, or an address bus through which transmission/reception of anaddress signal is performed. Such a signal wiring is typically called aglobal signal wiring. Furthermore, the substrate during the design phasemeans a virtual substrate constructed in a memory space of the CADsystem, and corresponds to a real semiconductor substrate or a realsemiconductor chip of an actual product (a semiconductor integratedcircuit).

[0007] Since the number of wiring layers is limited in semiconductorintegrated circuit design, when the areas above the function blocks areset as prohibition areas for the global signal wirings, the globalsignal wirings must bypass the function block perimeter. When the sizeof the function blocks is extremely large relative to the substratesize, the necessary length of the global signal wirings for bypassing isextremely long. The increased global signal wiring length may cause anoperation timing error (a timing violation), requiring redesigning.

[0008] In order to avoid an increase in wiring lengths, a design methodof limiting the wiring layers utilized for connecting within thefunction block to only a few layers from the bottom layer upward, andallocating global signal wirings to the upper wiring layers could beemployed. According to this design method, the global signal wirings maypass over the function block.

[0009] However, the following problems are not taken into account insuch a semiconductor integrated circuit design method.

[0010] The global signal wirings may pass over the function block withthe above design method; however additional buffering cells may not bearranged inside the function block in accordance with the global signalwiring passing route. In this case, the buffering cell is a circuit(intermediate cell) that amplifies a signal (increases drivingcapability) to be propagated through a global signal wiring.

[0011] Furthermore, since arrangement of buffering cells within thefunction block is impossible, arrangement of a buffering cell outside ofthe function block in the vicinity of each facing side of the functionblock, and connecting these buffering cells by means of the globalsignal wiring that passes over the function block is needed.Nevertheless, in the case of a function block of a huge size, the lengthof the global signal wiring that passes over the function block isextremely long, and the wiring capacitance thereof increases. Even if abuffering cell of high drive ability is arranged, the signalrising/falling time falls outside of design rule limitations, and timingerror occurs. That is to say, the wiring length that a buffering cellcan drive has a limit. So, in the case of a function block of a hugesize, since a global signal wiring that passes over the function blockcannot be arranged, a global signal wiring that bypasses the functionblock must be arranged.

[0012] Therefore, as shown in FIG. 1, basic structure of a semiconductorintegrated circuit according to a related art includes a function block2 upon a substrate 1, a first buffering cell 3 a, which is arranged inthe vicinity of a first side 2 a of the function block 2, a secondbuffering cell 3 b 1 and a third buffering cell 3 b 2, which is arrangedin the vicinity of a second side 2 b adjacent to the first side 2 a, anda fourth buffering cell 3 c, which is arranged in the vicinity of athird side 2 c adjacent to the second side 2 b. The first buffering cell3 a and the second buffering cell 3 b 1 are connected by signal wiring 4a that bypasses the function block 2. The second buffering cell 3 b 1and the third buffering cell 3 b 2 are connected by signal wiring 4 b.The third buffering cell 3 b 2 and the fourth buffering cell 3 c areconnected by signal wiring 4 c that bypasses the function block 2. Whenglobal signal wiring to bypass the function block 2 is long, by reasonof a limit to the wiring length that buffering cell 3 a to 3 c candrive, it is necessary to arrange a plurality of buffering cells betweenthe first buffering cell 3 a and the fourth buffering cell 3 c.

[0013] It should be noted that this type of semiconductor integratedcircuit design method is disclosed in U.S. Pat. No. 6,436,804 B2.

SUMMARY OF THE INVENTION

[0014] An aspect of the present invention inheres in a semiconductorintegrated circuit including a function block arranged on a substrate; afirst buffering cell arranged adjacent to a first side of the functionblock, a second buffering cell arranged adjacent to a second sideadjacent to the first side of the function block; and signal wiringpassing over the function block obliquely relative to the first side andthe second side, connecting the first buffering cell and the secondbuffering cell.

[0015] Another aspect of the present invention inheres in asemiconductor integrated circuit including a function block arranged ona substrate; a plurality of signal wirings having a length shorter thana length of a side of the function block on the substrate; a pluralityof buffering cells electrically connected in series between each of thesignal wirings; and a signal wiring passing obliquely across the cornerbetween a first side and a second side of the function block, whichconnects the buffering cells arranged adjacent to the first side andadjacent to the second side adjacent to the first side of the functionblock.

[0016] Still another aspect of the present invention inheres in asemiconductor integrated circuit including a function block arranged ona substrate; a plurality of buffering cells arranged regularly in thefunction block at an appointed interval; and a signal wiring extendingobliquely relative to a side of the function block, which is connectedbetween adjacent buffering cells.

[0017] Yet still another aspect of the present invention inheres in amethod of manufacturing a semiconductor integrated circuit, includingarranging a function block on a substrate; arranging a signal wiringwhich passes over the function block obliquely relative to a first sideand a second side adjacent to the first side of the function block; andarranging a first buffering cell connected to one end of the signalwiring, adjacent to the first side of the function block and a secondbuffering cell connected to another end of the signal wiring, adjacentto the second side of the function block.

[0018] Further aspect of the present invention inheres in a method ofmanufacturing a semiconductor integrated circuit, including arranging aplurality of function blocks on a substrate; extracting a first functionblock with minimum signal loss in the function blocks in a signal wiringroute; extracting a second function block arranged near the firstfunction block; arranging a signal wiring which passes obliquelyrelative to a first side and a second side adjacent to the first side ofthe second function block; determining whether a length of the signalwiring exceeds the signal wiring length limitation; determining whethera signal timing satisfies at least a design rule when the length of thesignal wiring exceeds the signal wiring length limitation; determiningwhether a buffering cell can be arranged when the signal timing fails tosatisfy the design rule; and arranging a first buffering cell connectedto one end of the signal wiring, adjacent to the first side of thesecond function block and a second buffering cell connected to anotherend of the signal wiring, adjacent to the second side of the secondfunction block.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a schematic view showing a basic structure of asemiconductor integrated circuit in the prior art;

[0020]FIG. 2 is a schematic view showing a first basic structure of asemiconductor integrated circuit according to a first embodiment of thepresent invention;

[0021]FIG. 3 is a schematic view showing a second basic structure of thesemiconductor integrated circuit according to the first embodiment ofthe present invention;

[0022]FIG. 4 is a schematic view showing a third basic structure of thesemiconductor integrated circuit according to the first embodiment ofthe present invention;

[0023]FIG. 5 is a schematic view showing a fourth basic structure of thesemiconductor integrated circuit according to the first embodiment ofthe present invention;

[0024]FIG. 6 is a plane view showing an example of a layout of astructure of the semiconductor integrated circuit according to the firstembodiment of the present invention;

[0025]FIG. 7A is a circuit diagram of a first basic structure of abuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0026]FIG. 7B is a plane view showing the first basic structure of thebuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0027]FIG. 8A is a circuit diagram of a second basic structure of abuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0028]FIG. 8B is a plane view showing the second basic structure of thebuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0029]FIG. 9A is a circuit diagram of a third basic structure of abuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0030]FIG. 9B is a plane view showing the third basic structure of thebuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0031]FIG. 10 is a circuit diagram of a fourth basic structure of abuffering cell of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0032]FIG. 11 is a plane view showing a first exemplary layout of asignal wiring of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0033]FIG. 12 is a plane view showing a second exemplary layout of thesignal wiring of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0034]FIG. 13 is a plane view showing a third exemplary layout of thesignal wiring of the semiconductor integrated circuit according to thefirst embodiment of the present invention;

[0035]FIG. 14 is a flowchart for explaining a fabrication method of thesemiconductor integrated circuit according to the first embodiment ofthe present invention;

[0036]FIG. 15 is a flowchart for explaining a substantial part of thefabrication method of the semiconductor integrated circuit according tothe first embodiment of the present invention;

[0037]FIG. 16 is a view showing schematic circuit configuration of a CADsystem executing the fabrication method of the semiconductor integratedcircuit according to the first embodiment of the present invention; and

[0038]FIG. 17 is a schematic view showing a configuration of a functionblock of a semiconductor integrated circuit according to a secondembodiment of the present invention;

[0039]FIG. 18 is a schematic view showing a basic structure of asemiconductor integrated circuit according to a third embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0040] Various embodiments of the present invention will be describedwith reference to the accompanying drawings. It is to be noted that thesame or similar reference numerals are applied to the same or similarparts and elements throughout the drawings, and the description of thesame or similar parts and elements will be omitted or simplified.

[0041] Generally and as it is conventional in the representation ofsemiconductor devices, it will be appreciated that the various drawingsare not drawn to scale from one figure to another nor inside a givenfigure.

[0042] In the following descriptions, numerous specific details are setfourth such as specific signal values, etc. to provide a thoroughunderstanding of the present invention. However, it will be obvious tothose skilled in the art that the present invention may be practicedwithout such specific details. In other instances, well-known circuitshave been shown in block diagram form in order not to obscure thepresent invention in unnecessary detail.

[0043] First Embodiment

[0044] (First Basic Structure of a Semiconductor Integrated Circuit)

[0045] As shown in FIG. 2, a first basic structure of a semiconductorintegrated circuit according to a first embodiment of the presentinvention includes a function block 2 arranged on a substrate 1, a firstbuffering cell 3 a, which is arranged in the vicinity of or adjacent toa first side 2 a of the function block 2, a second buffering cell 3 b,which is arranged in the vicinity of or adjacent to a second side 2 badjacent to the first side 2 a, and a signal wiring 4 a, which passesover the function block 2 obliquely relative to the first side 2 a andthe second side 2 b, connecting the first buffering cell 3 a and thesecond buffering cell 3 b.

[0046] Similarly, the semiconductor integrated circuit includes thefunction block 2 upon the substrate 1, the second buffering cell 3 b,which is arranged in the vicinity of or adjacent to the second side 2 bof the function block 2, a third buffering cell 3 c, which is arrangedin the vicinity of or adjacent to a third side 2 c adjacent to thesecond side 2 b, and a signal wiring 4 b, which passes over the functionblock 2 obliquely relative to the second side 2 b and the third side 2c, connecting the second buffering cell 3 b and the third buffering cell3 c.

[0047] In other words, the semiconductor integrated circuit includes thefunction block 2 upon the substrate 1, a plurality of the signal wirings4 a and 4 b, which have a shorter length than the length of sides 2 athrough 2 d of the function block 2, and a plurality of the bufferingcells 3 a to 3 c, which are electrically connected in series betweeneach of a plurality of the signal wirings 4 a and 4 b, and also includesat least a signal wiring 4 a, which connects the buffering cells 3 a and3 b arranged in the vicinity of or adjacent to the first side 2 a andthe second side 2 b adjacent to this first side 2 a of the functionblock 2, and passes obliquely across the corner between the first side 2a and the second side 2 b of the function block 2. The arrangementstructure for each of the function block 2, the buffering cells 3 b and3 c, and the signal wiring 4 b is also the same.

[0048] The semiconductor integrated circuit according to the firstembodiment herein is a semiconductor integrated circuit that employsstandard cell method and ASIC or the like, which are designed using aCAD system.

[0049] The photo masks are made based on this design data, and asemiconductor integrated circuit is fabricated as an actual product by asemiconductor fabrication process using these photo masks.

[0050] The substrate 1 is a semiconductor substrate (semiconductor chip)of, for example, a silicon single crystal or a compound semiconductorwith an actual product. The substrate 1 is a virtual substrate that isconstructed in a memory space of the CAD system during the design phase.

[0051] The function block 2 is a circuit block having one or a pluralityof specific functions, a logic function, a calculation function, amemory function or the like, and is a mega cell, a macro cell, a megablock, a macro block or the like. The function block 2, in the CADsystem design, is stored in a database as a piece of parts data, and canbe freely arranged and rearranged on the substrate. More concretely, acentral processing unit (CPU), read only memory (ROM) or random accessmemory (RAM) or the like corresponds to the function block 2.

[0052] With this semiconductor integrated circuit, intra-block wirings4× and 4 y are typically arranged inside the function block 2 and othercircuit blocks, but are not limited to being arranged only in thisregion. The intra-block wirings 4 x and 4 y are used to connectsemiconductor devices such as transistors, resistors, capacitors anddiodes that configure the function block 2, and may also connectcircuits configured with semiconductor devices, and may further be usedas power supply wiring, which supply power to the semiconductor devicesand circuits. In the multi-level wiring structure employed by thesemiconductor integrated circuit, the intra-block wirings 4 x and 4 yare allocated to several layers from the bottom layer upward on thesubstrate 1 side. For example, the intra-block wiring 4 x is allocatedto the first wiring layer (and/or the third wiring layer) extending inan X direction substantially parallel to the second side 2 b and thefourth side 2 d of the function block 2. The intra-block wiring 4 y isallocated to the second wiring layer (and/or the fourth wiring layer)extending in a Y direction substantially parallel to the first side 2 aand the third side 2 c of the function block 2. The intra-block wirings4 x and 4 y are electrically connected by connecting-hole interconnectssuch as through-hole interconnects or via interconnects not shown in thedrawings.

[0053] The intra-block wirings 4 x and 4 y are made of, for example, alow resistant wiring material such as aluminum (Al), an aluminum alloy(Al—Si, Al—Cu, Al—Cu—Si or the like), copper (Cu), or a copper alloy. Itshould be noted that the intra-block wiring 4 x is exemplary ‘firstsignal wiring’ according to the present embodiment, and the intra-blockwiring 4 y is exemplary ‘second signal wirings’ according to the presentembodiment.

[0054] The signal wirings 4 a and 4 b are arranged across the entiresubstrate, and are part of the signal wiring that passes over thefunction block 2 as the long global signal wiring. Signals to bepropagated through the signal wirings 4 a and 4 b are important forproviding circuit operation timing for data signals and address signalsin the entire semiconductor integrated circuit. The signal wirings 4 aand 4 b being arranged in, for example, the third wiring layer (or thefifth wiring layer), which is a layer higher than the intra-blockwirings 4 x and 4 y, is practical for passing obliquely over thefunction block 2. Furthermore, with the first basic structure, thesignal wiring 4 a may be arranged in the third wiring layer (or thefifth wiring layer), and the signal wiring 4 b may be arranged in thefourth wiring layer (or the sixth wiring layer). Moreover, the signalwiring 4 a may be arranged in the fourth wiring layer (or the sixthwiring layer), and the signal wiring 4 b may be arranged in the thirdwiring layer (or the fifth wiring layer). The wiring material for thesignal wirings 4 a and 4 b is the same as that for the intra-blockwirings 4 x and 4 y, for example. It should be noted that the signalwirings 4 a and 4 b are exemplary ‘signal wiring’ according to thepresent embodiment.

[0055] With the semiconductor integrated circuit according to the firstembodiment, an angle θ1 of the signal wiring 4 a relative to the secondside 2 b of the function block 2 or the intra-block wiring 4 x extendingdirection (wiring length direction) is set to 45 degrees. Obliquelyarranging the signal wiring 4 a as a signal wiring as such allows thesignal wiring 4 a length to be shortened to approximately 1/{squareroot}{square root over (2)} rather than when bypassing along the firstside 2 a and the second side 2 b as indicated by a dotted wiring in FIG.2. Similarly, an angle θ2 of the signal wiring 4 b relative to thesecond side 2 b of the function block 2 or the intra-block wirings 4 xextending direction is set to 45 degrees. The signal wiring 4 b may alsohave its length shortened to approximately 1/{square root}{square rootover (2)}.

[0056] As described above, the wiring length that the buffering cells 3a to 3 c can drive has a limit. Therefore, it is necessary to arrange atleast two buffering cells in between the buffering cell 3 a and thebuffering cell 3 c, when the wiring length that the buffering cells 3 ato 3 c can drive is larger than 2 times of the sum of length in the caseof the signal wirings 4 a and 4 b bypassing the circuit block 2.However, if the signal wirings 4 a and 4 b are oblique wiring, the sumof wiring length of the signal wirings 4 a and 4 b is shortened, and asa result, the number of buffering cell can be reduced.

[0057] Moreover, an insertion pitch for the buffering cells 3 a to 3 cto be electrically inserted in series for every constant wiring lengthmay also be shortened to approximately 1/{square root}{fraction (2)}along with the shortening of the lengths of the signal wirings 4 a and 4b. In other words, the lengths of the respective signal wirings 4 a and4 b become equivalent to the insertion pitch for the buffering cells 3 ato 3 c. For example, in the case of the size of the substrate 1 being a10 mm square, the lengths of the respective signal wirings 4 a and 4 bmay be set to 2 mm, and the insertion pitch for the buffering cells 3 ato 3 c may be set to 2 mm.

[0058] It should be noted that with the semiconductor integrated circuitaccording to the first embodiment, the buffering cells 3 a to 3 c arearranged outside of the function block 2. Basic cells not shown in thedrawing that can configure a specific basic circuit such as an invertercircuit or a NAND circuit are arranged outside of this function block 2in the design phase of the CAD system, and the buffering cells 3 a to 3c are configured with those basic cells. The detailed structure of thebuffering cells 3 a to 3 c is described later.

[0059] With the first basic structure of the semiconductor integratedcircuit according to the first embodiment structured in this manner, thebuffering cells 3 a and 3 b are arranged in the vicinity of or adjacentto the adjacent first side 2 a and the second side 2 b of the functionblock 2, respectively, and the signal wiring 4 a, which is connected tothese buffering cells 3 a and 3 b so as to pass obliquely over thefunction block 2, is arranged; thus, the wiring length of the signalwiring 4 a may be shortened, and the wiring capacitance may be reduced.Moreover, the driving capability of the buffering cell 3 a may berelatively increased as the wiring capacitance reduces. Similarly, thebuffering cells 3 b and 3 c are arranged in the vicinity of or adjacentto the adjacent second side 2 b and the third side 2 c of the functionblock 2, respectively, and the signal wiring 4 b, which is connected tothese buffering cells 3 b and 3 c so as to pass obliquely over thefunction block 2, is arranged; thus, the wiring length of the signalwiring 4 b may be shortened, and the wiring capacitance may be reduced.Moreover, the driving capability of the buffering cell 3 b may berelatively increased as the wiring capacitance reduces. Accordingly,since the global signal wiring that bypasses the function block 2 may bereduced, and signal delay may be prevented, a semiconductor integratedcircuit with excellent operating capability that is optimum for highintegration can be obtained.

[0060] It should be noted that with the semiconductor integrated circuitaccording to the first embodiment, both the angle θ1 of the signalwiring 4 a and the angle θ2 of the signal wiring 4 b are set to 45degrees and those signal wirings pass over the function block 2,however, the present embodiment is not limited to this angle. Thepresent embodiment may set the angles θ1 and θ2 to 30 degrees or 60degrees, for example. In any case, the angles θ1 and θ2 may beappropriately selected considering that they are manageable angles inthe CAD system, the sufficient fabrication process yield of thesemiconductor integrated circuit can be ensured, and suchabove-mentioned sufficient results can be obtained.

[0061] (Second Basic Structure of a Semiconductor Integrated Circuit)

[0062] A second basic structure of the semiconductor integrated circuitaccording to the first embodiment will be described using an exampleincluding a function block 2 with a form different than that of thefunction block 2 with the first basic structure. As shown in FIG. 3, thesemiconductor integrated circuit includes the function block 2 upon thesubstrate 1, the first buffering cell 3 a, which is arranged in thevicinity of or adjacent to the first side 2 a of the function block 2,the second buffering cell 3 b, which is arranged in the vicinity of oradjacent to the second side 2 b adjacent to the first side 2 a, and thesignal wiring 4 a, which passes obliquely over the function block 2relative to the first side 2 a and the second side 2 b, connecting thefirst buffering cell 3 a and the second buffering cell 3 b.

[0063] Similarly, the semiconductor integrated circuit includes thefunction block 2 upon the substrate 1, the third buffering cell 3 c,which is arranged in the vicinity of or adjacent to the second side 2 bof the function block 2, a fourth buffering cell 3 d, which is arrangedin the vicinity of or adjacent to the third side 2 c adjacent to thesecond side 2 b, and a signal wiring 4 c, which passes obliquely overthe function block 2 relative to the second side 2 b and the third side2 c, connecting the third buffering cell 3 c and the fourth bufferingcell 3 d.

[0064] The function block 2 with the second basic structure has either alarger planar size than that of the function block 2 with the firstbasic structure, or an oblong planar form with the second side 2 blonger than the first side 2 a. In other words, the function block 2having at least the second side 2 b sufficiently longer than the lengthof each of the signal wirings 4 a to 4 c, which are global signalwirings, is arranged in the semiconductor integrated circuit.

[0065] With the semiconductor integrated circuit including this functionblock 2, the signal wiring 4 a, which is the same as signal wiring 4 awith the first basic structure, and the signal wiring 4 c, which is thesame as signal wiring 4 b with the first basic structure, pass obliquelyover the function block 2, and the signal wiring 4 b is arranged outsideof the function block 2 substantially parallel to the second side 2 b.On the outside of the function block 2, the signal wiring 4 b connectsthe buffering cells 3 b and 3 c, which are arranged along the secondside 2 b apart from each other.

[0066] It is practical to arrange the signal wirings 4 a, 4 b and 4 c inthe same wiring layer (for example, the third or the fifth wiring layer)as in the first basic structure. Furthermore, each of the signal wirings4 a, 4 b and 4 c may be arranged in a separate wiring layer. Moreover,arranging the signal wirings 4 a and 4 c in the same wiring layer, andthe signal wiring 4 b in a separate wiring layer from the signal wirings4 a and 4 c is also possible.

[0067] The same results as obtained with the first basic structure canbe obtained with the second basic structure of the semiconductorintegrated circuit according to the first embodiment configured in thismanner.

[0068] (Third Basic Structure of a Semiconductor Integrated Circuit)

[0069] A third basic structure of the semiconductor integrated circuitaccording to the first embodiment is for describing an example where thesignal wirings 4 a and 4 b with the first basic structure are bus signalwiring. As shown in FIG. 4, the semiconductor integrated circuitincludes the function block 2 upon the substrate 1, first bufferingcells 30 a to 32 a, which are arranged in the vicinity of the first side2 a of the function block 2, second buffering cells 30 b to 32 b, whichare arranged in the vicinity of the second side 2 b adjacent to thefirst side 2 a, and signal wirings 40 a to 42 a, which pass obliquelyover the function block 2 relative to the first side 2 a and the secondside 2 b, connecting the first buffering cells 30 a to 32 a and thesecond buffering cells 30 b to 32 b, respectively.

[0070] Similarly, the semiconductor integrated circuit includes thefunction block 2 upon the substrate 1, the second buffering cells 30 bto 32 b, which are arranged in the vicinity of the second side 2 b ofthe function block 2, third buffering cells 30 c to 32 c, which arearranged in the vicinity of the third side 2 c adjacent to the secondside 2 b, and signal wirings 40 b to 42 b, which pass obliquely over thefunction block 2 relative to the second side 2 b and the third side 2 c,connecting the second buffering cells 30 b to 32 b and the thirdbuffering cells 30 c to 32 c, respectively.

[0071] The planar shape of the function block 2 with the third basicstructure is the same shape as that of the function block 2 with thefirst basic structure. Part of the signal wirings 40 a to 42 a and 40 bto 42 b of the global signal wirings such as data buses and addressbuses pass over the function block 2.

[0072] With the third basic structure shown in FIG. 4, since thebuffering cells 30 b to 32 b are aligned in the X direction along thesecond side 2 b, crossing wirings are necessary, and thus it ispractical to arrange the signal wirings 40 to 42 a and the signalwirings 40 b to 42 b in different wiring layers. It should be noted thatwhen the buffering cells 30 b to 32 b are aligned in the Y direction,crossing wiring is not necessary, and thus the signal wirings 40 a to 42a and the signal wirings 40 b to 42 b may be arranged in the same wiringlayer.

[0073] The same results as obtained with the first basic structure canbe obtained with the third basic structure of the semiconductorintegrated circuit according to the first embodiment configured in thismanner.

[0074] It should be noted that three signal wirings 40 a to 42 a andsignal wirings 40 b to 42 b have been described with the third basicstructure in order to simplify the description, however, there may betwo, four or more signal wirings. This is the same for a fourth basicstructure described later.

[0075] (Fourth Basic Structure of a Semiconductor Integrated Circuit)

[0076] The fourth basic structure of the semiconductor integratedcircuit according to the first embodiment is for describing an examplewhere the second and third basic structures are combined. As shown inFIG. 5, the semiconductor integrated circuit includes the function block2 upon the substrate 1, the first buffering cells 30 a to 32 a, whichare arranged in the vicinity of the first side 2 a of the function block2, the second buffering cells 30 b to 32 b, which are arranged in thevicinity of the second side 2 b adjacent to the first side 2 a, and thesignal wirings 40 a to 42 a, which pass obliquely over the functionblock 2 relative to the first side 2 a and the second side 2 b,connecting the first buffering cells 30 a to 32 a and the secondbuffering cells 30 b to 32 b, respectively.

[0077] Similarly, the semiconductor integrated circuit includes thefunction block 2 upon the substrate 1, the third buffering cells 30 c to32 c, which are arranged in the vicinity of the second side 2 b of thefunction block 2, fourth buffering cells 30 d to 32 d, which arearranged in the vicinity of the third side 2 c adjacent to the secondside 2 b, and signal wirings 40 c to 42 c, which pass obliquely over thefunction block 2 relative to the second side 2 b and the third side 2 c,connecting the third buffering cells 30 c to 32 c and the fourthbuffering cells 30 d to 32 d, respectively.

[0078] The signal wirings 40 a to 42 a and 40 c to 42 c are bus signalwirings and are global signal wirings like the signal wirings 40 a to 42a and 40 b to 42 b with the third basic structure.

[0079] The function block 2 with the fourth basic structure has either alarge planar size or an oblong planar shape in the same way as thefunction block 2 with the aforementioned second basic structure.

[0080] In the semiconductor integrated circuit including this functionblock 2, as with the signal wiring 4 b with the aforementioned secondbasic structure, the signal wirings 40 b to 42 b are arranged outside ofthe function block 2 substantially parallel along the second side 2 bthereof. Furthermore, on the outside of the function block 2, the signalwirings 40 b to 42 b connect the buffering cells 30 b to 32 b and 30 cto 32 c arranged along the second side 2 b apart from each other,respectively.

[0081] The same results as obtained with the first basic structure canbe obtained with the fourth basic structure of the semiconductorintegrated circuit according to the first embodiment configured in thismanner.

[0082] (A concrete Layout of a Semiconductor Integrated Circuit)

[0083] Next, a concrete layout structure of the semiconductor integratedcircuit according to the first embodiment is described. In this case,the semiconductor integrated circuit is one that employs standard cellmethod.

[0084] As shown in FIG. 6, a semiconductor integrated circuit 10includes a substrate 1, a plurality of input/output buffering cells 5,which are aligned along each side of the surrounding areas upon thesubstrate 1, and function blocks 20 to 22 and random logic rows 6, whichare arranged in the central area upon the substrate 1.

[0085] The input/output buffering cells 5 are interface circuits betweenthe semiconductor integrated circuit 10 interior and the exteriorthereof. The input/output buffering cells 5 comprise a plurality ofsemiconductor devices that can configure input interface circuits,output interface circuits, input/output interface circuits and the like(a layout structure thereof is not shown in the drawing.) Moreover, theinput/output buffering cells 5 comprise semiconductor devices includingat least transistors, resistors, and capacitors and the like that canconfigure input protection circuits and output protection circuits andthe like. Furthermore, the input/output buffering cells 5 compriseexternal terminals (bonding pads) not shown in the drawing.

[0086] The function blocks 20 to 22 have a function equivalent to thatof the function block 2 of the above-mentioned semiconductor integratedcircuit described in the first basic structure, and correspond to megacells or the like.

[0087] The random logic rows 6 are configured with a plurality of basiccells evenly aligned in the X direction. Each of these basic cells isarranged between wiring areas in the Y direction. Each basic cellincludes a plurality of semiconductor devices that can configure logiccircuits such as an inverter circuit or a NAND circuit by reconfiguringthe intra-block wirings 4 x and 4 y.

[0088] (First Basic Structure of a Buffering Cell)

[0089] Next, with the first basic structure of the semiconductorintegrated circuit, a concrete structure of the first through thirdbuffering cells 3 a to 3 c inserted between the signal wirings 4 a to 4c, which are global signal wirings, is described. It should be notedthat since the structure of the buffering cells 30 a, 31 a, 32 a and 3 ain the second through fourth basic structures of the semiconductorintegrated circuit are the same, descriptions thereof are omitted.Furthermore, in the description of the first through fourth basicstructures of the buffering cell 3 a, a generic reference numeral ‘3’ isattached to the buffering cells to avoid complicated reference numeralsand simplify description.

[0090] <Circuit Structure>

[0091] The buffering cell 3 with the first basic structure, as shown inFIG. 7A, is configured by two-step structure inverter circuits 301 and302, which are electrically connected in series between a signal inputterminal S1 and a signal output terminal S2.

[0092] The inverter circuit 301 is a front circuit connected directly tothe signal input terminal S1. This inverter circuit 301 is configuredwith an n-channel insulated gate field-effect transistor (hereafter,simply referred to as IGFET) Q11 and a p-channel IGFET Q21, which form acomplementary IGFET structure. Here, the IGFET denotes at least a metaloxide semiconductor field-effect transistor (MOSFET) and a metalinsulator semiconductor field-effect transistor (MISFET). The n-channelIGFET Q11 has a gate electrode connected to the signal input terminalS1, the source electrode connected to a reference power supply V_(ss),and the drain electrode connected to the drain electrode of thep-channel IGFET Q21. The reference power supply V_(ss) is a groundpotential, for example 0V, for the circuit. The p-channel IGFET Q21 hasa gate electrode connected to the signal input terminal S1, and thesource electrode connected to an operating power supply V_(dd). Theoperating power supply V_(dd) is an operating voltage, for example 1.7Vto 3.3 V, for the circuit.

[0093] The inverter circuit 302 is a subsequent circuit (a followingcircuit) connected directly to the signal input terminal S2. Thisinverter circuit 302 is a complementary IGFET including an n-channelIGFET Q12 and a p-channel IGFET Q22 as with the inverter circuit 301.The n-channel IGFET Q12 has a gate electrode connected to the drainelectrode of the n-channel IGFET Q11 and the p-channel IGFET Q21, thesource electrode connected to a reference power supply V_(ss), and thedrain electrode connected to the drain electrode of the p-channel IGFETQ22. The p-channel IGFET Q22 has a gate electrode connected to the drainelectrode of the n-channel IGFET Q11 and the p-channel IGFET Q21, andthe source electrode connected to an operating power supply V_(dd). Thedrain electrodes of the n-channel IGFET Q12 and the p-channel IGFET Q22are connected to the signal output terminal S2.

[0094] <Device Structure>

[0095] The aforementioned buffering cells 3 are configured with, forexample, the basic cells of the random logic rows 6 shown in FIG. 6.Herein, only the inverter circuit 301 to configure the buffering cell 3is described, and since the device structure of the inverter circuit 302is the same as that of the inverter circuit 301, description thereof isomitted.

[0096] As shown in FIG. 7B, the n-channel IGFET Q11 of the invertercircuit 301 is arranged in a p-well region 101 formed in the substrate 1surface, which is enclosed by an isolation insulating film 111. In otherwords, the n-channel IGFET Q11 includes the p-well region 101, which isused as an active region, a gate insulator (not shown in the drawing)arranged on this p-well region 101, a gate electrode 112 arranged on thegate insulator, and a pair of n-type semiconductor regions 113, whichare used as the source and drain regions arranged on both sides alongthe length of the gate electrode 112.

[0097] A single layer film made from either a silicon oxide layer, asilicon nitride film or an oxynitride film, or a compound film thereofmay be practically used as the gate insulator. A single layer film madefrom either a silicon polycrystalwiring film, a refractory metal film,or a refractory metal silicide film, or a compound film layered with arefractory metal film, or a refractory metal silicide film upon asilicon polycrystalwiring film may be practically used as the gateelectrode 112. A lightly doped drain (LDD) structure may be practicallyused for the n-type semiconductor region 113.

[0098] The p-channel IGFET Q21 is arranged in an n-well region 102formed in the substrate 1 surface, which is enclosed by the isolationinsulating film 111. In other words, the n-channel IGFET Q21 includesthe n-well region 102, which is used as an active region, a gateinsulator not shown in the drawing arranged on this n-well region 102, agate electrode 112 arranged on the gate insulator, and a pair of p-typesemiconductor regions 114, which are used as the source and drainregions arranged on both sides along the length of the gate electrode112. The practical materials for the gate insulator and the gateelectrode and the practical structure of the p-type semiconductor region114 are the same as with the n-channel IGGET Q11.

[0099] In the random logic rows 6, an intra-cell power supply wiring(V_(ss)) 401 and an intra-cell operating power supply wiring (V_(dd))402 are arranged extending in the X direction. The intra-cell powersupply wiring (V_(ss)) 401 is connected to the n-type semiconductorregion (source region) 113 of the n-channel IGFET Q11 through anintra-cell wiring 403. The intra-cell operating power supply wiring 402is connected to the p-type semiconductor region (source region) 114 ofthe p-channel IGFET Q21 through an intra-cell wiring 403. Furthermore,the gate electrodes 112 of the n-channel IGFET Q11 and the p-channelIGFET Q21 are connected, respectively, to the signal input terminal S1through an intra-cell wiring 403, and the drain region is connected tothe subsequent circuit 302. The intra-cell power supply wiring 401, theintra-cell operating power supply wiring 402 and the intra-cell wirings403 are arranged in the first wiring layer and are made of, for example,an aluminum alloy (Al—Si, Al—Cu, Al—Cu—Si or the like).

[0100] (Second Basic Structure of a Buffering Cell)

[0101] A buffering cell 3 with a second basic structure is one withdouble the driving capability of the buffering cell 3 with the firstbasic structure.

[0102] <Circuit Structure>

[0103] The buffering cell 3 with the second basic structure, as shown inFIG. 8A, is configured by two-step structure inverter circuits 301 and302, which are electrically connected in series between the signal inputterminal S1 and the signal output terminal S2.

[0104] The inverter circuit 301 is a front circuit connected directly tothe signal input terminal S1. This inverter circuit 301 has a two-stepstructure where the drain electrodes of the n-channel IGFET Q11 and thep-channel IGFET Q21 and the drain electrodes of the n-channel IGFET Q12and the p-channel IGFET Q22 are electrically connected, respectively.Each of the n-channel IGFET Q11 and Q12 has a gate electrode connectedto the signal input terminal S1, the source electrode connected to areference power supply V_(ss), and the drain electrode connected to thedrain electrode of the p-channel IGFET Q21 and Q22. Each of thep-channel IGFET Q21 and Q22 has a gate electrode connected to the signalinput terminal S1, and the source electrode connected to an operatingpower supply V_(dd).

[0105] The inverter circuit 302 is a subsequent circuit connecteddirectly to the signal output terminal S2. This inverter circuit 302,similar to the inverter circuit 301, has a two-step structure where thedrain electrodes of an n-channel IGFET Q13 and a p-channel IGFET Q23 andthe drain electrodes of an n-channel IGFET Q14 and a p-channel IGFET Q24are electrically connected, respectively. Each of the n-channel IGFETQ13 and Q14 has a gate electrode connected to the inverter circuit 301(the drain electrodes of IGFET Q11, Q12, Q21, and Q22), a sourceelectrode connected to a reference power supply V_(ss), and a drainelectrode connected to the drain electrodes of the p-channel IGFET Q23and Q24. Each of the p-channel IGFET Q23 and Q24 has a gate electrodeconnected to the signal input terminal S1, and a source electrodeconnected to an operating power supply V_(dd). The drain electrodes ofthe n-channel IGFET Q13 and Q14 and the p-channel IGFET Q23 and Q24 areconnected to the signal output terminal S2.

[0106] <Device Structure>

[0107] Herein, as with the buffering cell 3 having the first basicstructure, only the inverter circuit 301 of the buffering cell 3 isdescribed, and description of the inverter circuit 302 is omitted.

[0108] The n-channel IGFET Q11 and Q12 of the inverter circuit 301, asshown in FIG. 8B, are arranged with their gate width directions inaccordance, facing the Y direction adjacent to each other. The n-channelIGFET Q11 and Q12 are both arranged in the p-well region 101 formed inthe substrate 1 surface, which is enclosed by the isolation insulatingfilm 111. In other words, each of the n-channel IGFET Q11 and Q12includes the p-well region 101, which is used as an active region, agate insulator (not shown in the drawing) arranged on this p-well region101, a gate electrode 112 arranged on the gate insulator, and a pair ofn-type semiconductor regions 113, which are used as the source and drainregions arranged on both sides along the length of the gate electrode112.

[0109] The p-channel IGFET Q21 and Q22 are arranged with their gatewidth directions in accordance, facing the Y direction adjacent to eachother. The p-channel IGFET Q21 and Q22 are both arranged in the n-wellregion 102 formed in the substrate 1 surface, which is enclosed by theisolation insulating film 111. In other words, each of the p-channelIGFET Q21 and Q22 includes the n-well region 102, which is used as anactive region, a gate insulator (not shown in the drawing) arranged onthis n-well region 102, a gate electrode 112 arranged on the gateinsulator, and a pair of n-type semiconductor regions 114, which areused as the source and drain regions arranged on both sides along thelength of the gate electrode 112.

[0110] It should be noted that the practical materials for the gateinsulator and gate electrodes of the n-channel IGFET Q11 and Q12 and thep-channel IGFET Q21 and Q22, as well as the practical structure of then-type semiconductor region 113 and the p-type semiconductor region 114are the same as for the n-channel IGFET Q11 and the p-channel IGFET Q21with the first basic structure. Furthermore, the intra-cell power supplywiring 401, the intra-cell operating power supply wiring 402 and theintra-cell wirings 403 are similar to the intra-cell reference powersupply wiring 401 with the first basic structure, only differing intheir wire connection patterns.

[0111] (Third Basic Structure of a Buffering Cell)

[0112] A buffering cell 3 with a third basic structure is one withtriple the driving capability of the buffering cell 3 with the firstbasic structure.

[0113] <Circuit Structure>

[0114] The buffering cell 3 with the third basic structure, as shown inFIG. 9A, is configured by the two-step structure inverter circuits 301and 302, which are electrically connected in series between the signalinput terminal S1 and the signal output terminal S2.

[0115] The inverter circuit 301 is a front circuit connected directly tothe signal input terminal S1, and basically has the same structure asthe inverter circuit 301 of the buffering cell 3 with the second basicstructure. Namely, the inverter circuit 301 has a two-step structurewhere the drain electrodes of the n-channel IGFET Q11 and the p-channelIGFET Q21 and the drain electrodes of the n-channel IGFET Q12 and thep-channel IGFET Q22 are electrically connected, respectively. Each ofthe n-channel IGFET Q11 and Q12 has a gate electrode connected to thesignal input terminal S1, a source electrode connected to a referencepower supply V_(ss), and a drain electrode connected to the drainelectrode of the p-channel IGFET Q21 and Q22. Each of the p-channelIGFET Q21 and Q22 has a gate electrode connected to the signal inputterminal S1, and a source electrode connected to an operating powersupply V_(dd).

[0116] The inverter circuit 302 is a subsequent circuit connecteddirectly to the signal output terminal S2. This inverter circuit 302 hasa three-step structure where the drain electrodes of the n-channel IGFETQ113 and the p-channel IGFET Q23, the drain electrodes of the n-channelIGFET Q14 and the p-channel IGFET Q24, and the drain electrodes of ann-channel IGFET Q15 and a p-channel IGFET Q25 are electricallyconnected, respectively. Each of the n-channel IGFET Q13, Q14 and Q15has a gate electrode connected to the inverter circuit 301 (the drainelectrode of IGFET Q11, Q12, Q21, and Q22), a source electrode connectedto a reference power supply V_(ss), and a drain electrode connected tothe drain electrode of the p-channel IGFET Q23 and Q24. Each of thep-channel IGFET Q23, Q24 and Q25 has a gate electrode connected to thesignal input terminal S1, and a source electrode connected to anoperating power supply V_(dd). The drain electrodes of the n-channelIGFET Q13 to Q15 and the p-channel IGFET Q23 to Q25 are connected to thesignal output terminal S2.

[0117] <Device Structure>

[0118] The basic structure of inverter circuit 301 of the buffering cell3 is the same as that of the inverter circuits 301 and 302 of thebuffering cell 3 with the second basic structure, and thus only theinverter circuit 302 of the buffering cell 3 is described here, anddescription of the inverter circuit 301 is omitted.

[0119] The n-channel IGFET Q13, Q14 and Q15 of the inverter circuit 302,as shown in FIG. 9B, are arranged with their gate width directions inaccordance, facing the Y direction adjacent to each other. The n-channelIGFET Q13, Q14 and Q15 are all arranged in the p-well region 101 formedin the substrate 1 surface, which is enclosed by the isolationinsulating film 111. In other words, the n-channel IGFET Q13, Q14 andQ15 include the p-well region 101, which is used as an active region, agate insulator not shown in the drawing arranged on this p-well region1, a gate electrode 112 arranged on the gate insulator, and a pair ofn-type semiconductor regions 113, which are used as the source and drainregions arranged on both sides along the length of the gate electrode112.

[0120] The p-channel IGFET Q23, Q24 and Q25 are arranged with their gatewidth directions in accordance, and the n-channel IGFET Q13, Q14 and Q15are arranged with their gate width directions in accordance, facing theY direction adjacent to each other, respectively. The p-channel IGFETQ23, Q24 and Q25 are all arranged in the n-well region 102 formed in thesubstrate 1 surface, which is enclosed by the isolation insulating film111. In other words, the p-channel IGFET Q23, Q24 and Q25 include then-well region 102, which is used as an active region, a gate insulatornot shown in the drawing arranged on this p-well region 1, a gateelectrode 112 arranged on the gate insulator, and a pair of p-typesemiconductor regions 113, which are used as the source and drainregions arranged on both sides along the length of the gate electrode112.

[0121] It should be noted that the practical materials for the gateinsulator and gate electrodes of the n-channel IGFET Q13, Q14 and Q15and the p-channel IGFET Q23, Q24 and Q25, as well as the practicalstructure of the n-type semiconductor region 113 and the p-typesemiconductor region 114 are the same as with the n-channel IGFET Q11and the p-channel IGFET Q21 having the first basic structure.Furthermore, the intra-cell power supply wiring (V_(ss)) 401, theintra-cell operating power supply wiring (V_(dd)) 402 and the intra-cellwirings 403 are similar to intra-cell reference power supply wiring 401with the first basic structure only differing in their wire connectionpatterns.

[0122] (Fourth Basic Structure of a Buffering Cell)

[0123] A buffering cell 3 with a fourth basic structure has triple thedriving capabilities of both the inverter circuits 301 and 302 in thebuffering cell 3 with the first basic structure.

[0124] <Circuit Structure>

[0125] The buffering cell 3 with the fourth basic structure, as shown inFIG. 10, is configured by the two-step structure inverter circuits 301and 302, which are electrically connected in series between the signalinput terminal S1 and the signal output terminal S2.

[0126] The inverter circuit 301 is a front circuit connected directly tothe signal input terminal S1, and basically has the same structure asthe inverter circuit 302 of the buffering cell 3 with the third basicstructure. Namely, the inverter circuit 301 has a three-step structurewhere the drain electrodes of the n-channel IGFET Q11 and the p-channelIGFET Q21, the drain electrodes of the n-channel IGFET Q12 and thep-channel IGFET Q22, and the drain electrodes of an n-channel IGFET Q13and a p-channel IGFET Q23 are electrically connected, respectively. Eachof the n-channel IGFET Q11, Q12 and Q13 has a gate electrode connectedto the signal input terminal S1, a source electrode connected to areference power supply V_(ss), and a drain electrode connected to thedrain electrodes of the p-channel IGFET Q21, Q22 and Q23. Each of thep-channel IGFET Q21, Q22 and Q23 has a gate electrode connected to thesignal input terminal S1, and a source electrode connected to anoperating power supply V_(dd).

[0127] The inverter circuit 302 is a subsequent circuit connecteddirectly to the signal input terminal S2, and basically has the samestructure as the inverter circuit 302 of the buffering cell 3 with thethird basic structure. The inverter circuit 302 has a three-stepstructure where the drain electrodes of the n-channel IGFET Q14 and thep-channel IGFET Q24, the drain electrodes of the n-channel IGFET Q15 andthe p-channel IGFET Q25, and the drain electrodes of an n-channel IGFETQ16 and a p-channel IGFET Q26 are electrically connected, respectively.Each of the n-channel IGFET Q14, Q15 and Q16 has a gate electrodeconnected to the inverter circuit 301 (the drain electrode of IGFET Q11,Q12, Q13, Q21, Q22 and Q23), a source electrode connected to a referencepower supply V_(ss), and a drain electrode connected to the drainelectrodes of the p-channel IGFET Q24, Q25 and Q26. Each of thep-channel IGFET Q24, Q25 and Q26 has a gate electrode connected to thesignal input terminal S1, and a source electrode connected to anoperating power supply V_(dd). The drain electrodes of the n-channelIGFET Q14 to Q16 and the p-channel IGFET Q24 to Q26 are connected to thesignal output terminal S2.

[0128] <Device Structure>

[0129] The basic structure of inverter circuits 301 and 302 of thebuffering cell 3 is the same as that of the inverter circuit 302 of thebuffering cell 3 with the third basic structure, and thus description ofthe device structure thereof is omitted.

[0130] (Another Basic Structure of a Buffering Cell)

[0131] As mentioned before, the structure of the buffering cell 3 can beappropriately modified. For example, when the global signal wiring isrelatively long and the wiring load is large, at least the invertercircuit 302 of the buffering cell 3 can be configured by a four- or morestep structure. Furthermore, in the case of enhancing the drivingcapability, at least the IGFET Q gate width of the final output phase ofthe inverter circuit 302 may be longer than the other IGFET Q gatewidth.

[0132] (First Exemplary Layout of Signal Lines)

[0133] Next, a first exemplary layout of global signal wirings in asemiconductor integrated circuit 10 is shown in FIG. 11. Here, forsimplification of description, an example of two global signal wirings4A and 4B being conveniently arranged is described.

[0134] The function blocks 23 and 24 are arranged upon the substrate 1of the semiconductor integrated circuit 10. In FIG. 11, the globalsignal wiring 4A, which extends from an input/output buffering cell 5Aarranged on the left side of the substrate 1, passes obliquely over thefunction block 23, and extends across an extensive range until reachingclose to the right side of the substrate 1. A part of a signal wiring 4a of the global signal wiring 4A passing over the function block 23 isarranged obliquely relative to the first side 2 a and the second side 2b of the function block 23. A buffering cell 3 a is arranged in thevicinity of or adjacent to the first side 2 a of the function block 23,and a buffering cell 3 b is arranged in the vicinity of or adjacent tothe second side 2 b. One end of the signal wiring 4 a is electricallyconnected to the buffering cell 3 a, and the other end is electricallyconnected to the buffering cell 3 b.

[0135] Similarly, the global signal wiring 4B, which extends from aninput/output buffering cell 5B arranged on the left side of thesubstrate 1, passes over the function block 24 at an angle, and extendsacross an extensive range until reaching close to the right side of thesubstrate 1. A part of the signal wiring 4 a of the global signal wiring4B passing over the function block 24 is arranged obliquely relative tothe first side 2 a and the second side 2 b of the function block 24. Abuffering cell 3 a is arranged in the vicinity of or adjacent to thefirst side 2 a of the function block 24, and a buffering cell 3 b isarranged in the vicinity of or adjacent to the second side 2 b. One endof the signal wiring 4 a is electrically connected to the buffering cell3 a, and the other end is electrically connected to the buffering cell 3b.

[0136] With the semiconductor integrated circuit 10, which includes sucha first layout of global signal wiring, the wiring length of the globalsignal wirings 4A and 4B can be shortened, and the wiring capacitancecan be reduced due to the signal wiring 4 a passing over the functionblocks 23 and 24. The number of necessary buffering cells can be reducedin the global signal wiring 4A by shortening the wiring length of globalsignal wiring 4A. Similarly, the number of necessary buffering cells canbe reduced in the global signal wiring 4 B by shortening the wiringlength of global signal wiring 4B. In addition, structure of bufferingcell 3 can be optimized depending on wiring capacitance, and electricitycomposed and an area of a buffering cell can be reduced. Moreover, thedriving capability of the buffering cell 3 a may be relatively increasedas the wiring capacitance reduces. Accordingly, since the frequency ofthe global signal wiring 4A bypassing the function block 23 may bereduced, the frequency of the global signal wiring 4B bypassing thefunction block 24 may be reduced, and signal delay may be prevented, thesemiconductor integrated circuit 10 with excellent operating capabilitythat is optimum for high integration can be provided.

[0137] (Second Exemplary Layout of Signal wirings)

[0138] Next, a second exemplary layout of global signal wiring in thesemiconductor integrated circuit 10 is shown in FIG. 12. The secondlayout is one for describing an example that moderates or dispersessignal wiring hotspots between function blocks. In the followingdescription, a ‘hotspot’ is an area where signal wiring is crowded. Itshould be noted that the second layout is not limited to only globalsignal wiring, and may be applied to the layout for signal wiring andpower supply wiring arranged between function blocks.

[0139] In the semiconductor integrated circuit 10, a function block 25is arranged at the lower left of the substrate 1, a function block 26 isarranged at the upper left, a function block 27 is arranged at the upperright, and a function block 28 is arranged at the lower right. It shouldbe noted that the case of four function blocks 25 to 28 beingconveniently arranged is described; however, the number of functionblocks to be arranged is not limited thereto. The function block 25outputs a predetermined signal to the function block 27, which isarranged at the upper right as viewed from the function block 25,through signal wirings 4C and 4D. The signal wiring 4C extends from thefunction block 25 to the right side (X direction), passes obliquely overthe function block 28, which is arranged on the right side as viewedfrom the function block 25, and then extends to the upper side (Ydirection), connecting to the function block 27. A buffering cell 30 ais arranged in the vicinity of or adjacent to the first side 2 a of thefunction block 28, and a buffering cell 30 b is arranged in the vicinityof or adjacent to the second side 2 b. One end of the signal wiring 40a, which is a part of the signal wiring 4C and passes over the functionblock 28, is connected to the buffering cell 30 a, and the other end isconnected to the buffering cell 30 b. Similarly, the signal wiring 4Dextends from the function block 25 to the right side, passes obliquelyover the function block 28, and extends to the upper side, connecting tothe function block 27. A buffering cell 31 a is arranged in the vicinityof or adjacent to the first side 2 a of the function block 28, and abuffering cell 31 b is arranged in the vicinity of or adjacent to thesecond side 2 b. One end of the signal wiring 41 a, which is a part ofthe signal wiring 4D and passes over the function block 28, is connectedto the buffering cell 31 a, and the other end is connected to thebuffering cell 31 b.

[0140] Furthermore, the function block 27 outputs a predetermined signalto the function block 25 through signal wirings 4E, 4F, 4G and 4H. Thesignal wirings 4E and 4F pass between the four function blocks 25 to 28,namely hotspots that easily become congested with signal wiring.

[0141] The signal wiring 4G extends from the function block 27 to theleft side (X direction), passes obliquely over the function block 26,which is arranged on the left side as viewed from the function block 27,and then extends to the lower side (Y direction), connecting to thefunction block 25. A buffering cell 30 a is arranged in the vicinity ofthe third side 2 c of the function block 26, and a buffering cell 30 bis arranged in the vicinity of the fourth side 2 d. One end of thesignal wiring 40 a, which is a part of the signal wiring 4G and whichpasses over the function block 26, is connected to the buffering cell 30a, and the other end is connected to the buffering cell 30 b. Similarly,the signal wiring 4H extends from the function block 27 to the leftside, passes obliquely over the function block 26, and then extends tothe lower side, connecting to the function block 25. A buffering cell 31a is arranged in the vicinity of the third side 2 c of the functionblock 28, and a buffering cell 31 b is arranged in the vicinity of thefourth side 2 d. The signal wiring 41 a, which is a part of the signalwiring 4H and passes over the function block 26, is connected to one endof the buffering cell 31 a, and the other end is connected to thebuffering cell 31 b.

[0142] The function block 25 and the function block 26, which isarranged on the upper side as viewed from the function block 25, aredirectly connected through signal wirings 41 and 4J. Here, when thewiring lengths of the signal wirings 41 and 4J are shorter than those ofthe signal wirings 4E and 4F, and the driving capability of the finaloutput phase circuit of the function blocks 25 and 26 is sufficient, abuffering cell 3 need not be arranged in between the signal wirings 41and 4J.

[0143] Moreover, the function block 26 outputs a predetermined signal tothe function block 28, which is arranged at the lower right as viewedfrom the function block 26, through signal wirings 4K, 4L and 4M. Thesignal wiring 4K extends from the function block 26 to the right side (Xdirection), passes obliquely over the function block 27, which isarranged on the right side as viewed from the function block 26, andthen extends to the lower side (Y direction), connecting to the functionblock 28. A buffering cell 30 a is arranged in the vicinity of the firstside 2 a of the function block 27, and a buffering cell 30 b is arrangedin the vicinity of the fourth side 2 d. One end of the signal wiring 40a, which is a part of the signal wiring 4K and passes over the functionblock 27, is connected to the buffering cell 30 a, and the other end isconnected to the buffering cell 30 b. Similarly, the signal wiring 4Lextends from the function block 26 to the right side, passes obliquelyover the function block 27, and then extends to the lower side,connecting to the function block 28. A buffering cell 31 a is arrangedin the vicinity of the first side 2 a of the function block 27, and abuffering cell 31 b is arranged in the vicinity of the fourth side 2 d.One end of the signal wiring 41 a, which is a part of the signal wiring4L and passes over the function block 27, is connected to the bufferingcell 31 a, and the other end is connected to the buffering cell 31 b.The signal wiring 4M extends from the function block 26 to the rightside, passes obliquely over the function block 27, and then extends tothe lower side, connecting to the function block 28. A buffering cell 32a is arranged in the vicinity of the first side 2 a of the functionblock 27, and a buffering cell 32 b is arranged in the vicinity of thefourth side 2 d. One end of the signal wiring 42 a, which is a part ofthe signal wiring 4M and passes over the function block 27, is connectedto the buffering cell 32 a, and the other end is connected to thebuffering cell 32 b.

[0144] With the semiconductor integrated circuit 10 according to thefirst embodiment configured in this manner, the signal wirings 40 a and41 a, which are part of the signal wirings 4C and 4D, respectively, passobliquely over the function block 28, the signal wirings 40 a and 41 a,which are part of the signal wirings 4G and 4H, respectively, passobliquely over the function block 26, and the signal wirings 40 a, 41 aand 42 a, which are part of the signal wirings 4K, 4L and 4M,respectively, pass obliquely over the function block 27, allowingreduction or dispersion of signal wiring hotspots between functionblocks.

[0145] Moreover, with the semiconductor integrated circuit 10, reducingbypassing signal wirings, which are routed around the perimeter of thefunction blocks 25 to 28, while dispersing hotspots is possible, therebyallowing control of signal transmission delay and implementation ofhigh-speed circuit operation. In addition, buffering cell numericalreduction is possible by reducing the length of the bypassing signalwiring. Electricity consumption and an area of a buffering cell can bereduced because a structure of a buffering cell can be optimizedaccording to the decrease in wiring capacitance.

[0146] Furthermore, with the semiconductor integrated circuit 10,arrangement regions for the signal wirings may be utilized effectivelydue to the dispersion of the hotspots, thereby improving integration.

[0147] (Third Exemplary Layout of Signal Lines)

[0148] Next, a third exemplary layout of global signal wirings in thesemiconductor integrated circuit 10 is shown in FIG. 13. The thirdlayout is one for describing an example that has various global signalwirings pass obliquely over a single function block as long as thewiring length limitation allows. It should be noted that the thirdlayout, as with the second layout, is not limited to only global signalwiring, and may be applied to a layout for signal wiring and powersupply wiring arranged between function blocks.

[0149] With the semiconductor integrated circuit 10 shown in FIG. 13, afunction block 2 is arranged in the upper left corner upon the substrate1, and input/output buffering cells 5 are arranged along the first side(left side) 2 a and the second side (upper side) 2 b of the functionblock 2.

[0150] Signal wirings 4O and 4P, which extend to the lower side, passobliquely over the function block 2 from upper left to lower right, andthen extend to the right side, are connected to an input/outputbuffering cell 5C arranged on the upper side. Since the drivingcapability of the output circuit of the input/output buffering cell 5Cis typically higher than that of the output of a logic circuit in thefunction block 2 not shown in the drawing, a buffering cell 3 is notparticularly necessary near the second side 2 b of the function block 2when passing over the function block 2 directly from the input/outputbuffering cell 5C. The signal wiring 40 a of the signal wiring 40 thatpasses over the function block 2 is arranged obliquely from the secondside 2 b towards the third side 2 c, connecting to the buffering cell 30a. The signal wiring 41 a of the signal wiring 4P that passes over thefunction block 2 is arranged obliquely from the second side 2 b towardsthe third side 2 c, connecting to the buffering cell 31 a.

[0151] Meanwhile, signal wirings 4Q, 4R and 4S, which extend to theright side, pass obliquely over the same function block 2 from upperleft to lower right, and then extend to the lower side, are connected toan input/output buffering cell 5D arranged on the left side. A bufferingcell 3 is not particularly necessary near the first side 2 a of thefunction block 2. The signal wiring 40 a of the signal wiring 4Q thatpasses over the function block 2 is arranged obliquely from the firstside 2 a towards the fourth side 2 d, connecting to the buffering cell30 a. Similarly, the signal wiring 41 a of the signal wiring 4R thatpasses over the function block 2 is arranged obliquely from the firstside 2 a towards the fourth side 2 d, connecting to the buffering cell31 a. The signal wiring 42 a of the signal wiring 4S that passes overthe function block 2 is arranged obliquely from the first side 2 atowards the fourth side 2 d, connecting to the buffering cell 32 a.

[0152] It should be noted that in FIG. 13, a signal wiring (or globalsignal wiring) 4T extends towards the right side from an input/outputbuffering cell 5F arranged on the upper side, and a signal wiring (orglobal signal wiring) 4U extends toward the lower side from aninput/output buffering cell 5E arranged on the left side. These signalwirings 4T and 4U are orthogonal wirings, but however do not passobliquely over the function block 2 so as to satisfy the constraint forthe wiring length.

[0153] With the semiconductor integrated circuit 10 according to thefirst embodiment configured in this manner, the same results as with thesecond layout may be obtained, as well as arranging multiple types ofglobal signal wirings including the signal wirings 40 and 4P, which passobliquely over the upper right corner of the function block 2, and thesignal wirings 4Q, 4R, and 4S, which pass obliquely over the lower leftcorner.

[0154] (Semiconductor Integrated Circuit Fabrication Method)

[0155] An example of a fabrication method of the semiconductorintegrated circuit 10, particularly a fabrication method of thesemiconductor integrated circuit 10, which includes a global signalwiring fabrication method using a CAD system, is described referencingthe flowcharts shown in FIG. 14 and FIG. 15, and a configuration of theCAD system shown in FIG. 16.

[0156] The CAD system shown in FIG. 16 includes a CPU 500, a databaseunit 600, a main memory unit 700, an input unit 810, and an output unit820. Moreover, the CPU 500 includes an input data module 501, a circuitarrangement module 502, a clock signal wiring module 503, a power supplywiring module 504, a global wiring module 505, a block extraction module506, an evaluation module 507, a buffering cell module 508, and aninspection module 509. The input data module 501 creates input files byreading out necessary data from the database unit 600 and the mainmemory unit 700 in order for the CAD system to make a photo mask(reticle). The circuit arrangement module 502 arranges function blocksand the like based on the input file information. The clock signalwiring module 503 arranges clock signal wiring. The power supply wiringmodule 504 arranges power supply wiring. The global wiring module 505arranges global signal wiring. The block extraction module 506 extractscircuit blocks existing along a global signal wiring route. Theevaluation module 507 evaluates the global signal wiring based on apredetermined design rule. The buffering cell module 508 determineswhether or not to arrange a buffering cell along a global signal wiringroute. The inspection module 509 inspects electrical characteristics ofglobal signal wiring. The database unit 600 includes a parts data memorydomain 601 and a design rule memory domain 602. The parts data memorydomain 601 stores parts data information for circuit blocks and thelike. The design rule memory domain 602 stores predetermined designrules for circuit arrangement and wiring. The main memory unit 700includes a circuit data memory domain 701, an arrangement data memorydomain 702, and a mask data memory domain 703. The circuit data memorydomain 701 stores information for designing semiconductor integratedcircuits. The arrangement data memory domain 702 stores arrangementinformation for semiconductor integrated circuit being designed. Themask data memory domain 703 stores information for circuit arrangementsand wiring and the like generated by the CAD system.

[0157] With the CAD system shown in FIG. 16, information necessary fordesigning the semiconductor integrated circuit, which is input throughthe input unit 810, is stored in the database unit 600 and the mainmemory unit 700. The CPU 500 can perform circuit arrangement and wiringthat satisfies design rules, store information necessary for making thephoto masks (reticles) in the main memory unit 700, and retrieve itthrough the output unit 820.

[0158] (1) To begin with, various information stored in the databaseunit 600 and the main memory unit 700 through the input unit 810necessary for designing the semiconductor integrated circuit is read bythe input data module 501, creating an input file (S10). The createdinput file is stored in the arrangement data memory domain 702.

[0159] (2) The circuit arrangement module 502 reads circuit informationstored in the arrangement data memory domain 702, arranging a functionblock 2 upon the substrate 1 (see the layout for the semiconductorintegrated circuit 10 shown in FIG. 6). In this case, a function blockincludes at least a mega cell, as mentioned earlier.

[0160] (3) Next, the circuit arrangement module 502 uses as the randomlogic rows 6 a region in which the function block 2 is not arranged uponthe substrate 1, arranging a logic circuit in these random logic rows 6(S12).

[0161] (4) The clock signal wiring module 503 reads out the circuitinformation stored in the arrangement data memory domain 702, arranginga clock signal wiring upon the substrate 1 (S13). The clock signalwiring is arranged prior to power supply wiring and signal wiring inorder to allow the system to operate at a high speed. It is practical toarrange the clock signal wiring using the top wiring layer, which cannotbe easily restricted by the layout.

[0162] (5) The power supply wiring module 504 reads the circuitinformation stored in the arrangement data memory domain 702, arranginga power supply wiring upon the substrate 1 (S14). The power supplywiring is typically arranged with one set of a reference power supplywiring V_(ss), which supplies a circuit reference power supply of 0V,for example, and an operating power supply wiring V_(dd), which suppliesa circuit operating power supply of 3.3V to 5V, for example. The powersupply wiring is arranged, for example, in the second wiring layer as afixed pattern extending along the outer edge of the substrate 1 on theinput/output buffering cells 5. Furthermore, the power supply wiring isarranged, for example, in the second wiring layer on the random logicrows 6 in the basic cell arranging direction. Moreover, the power supplywiring is arranged in a large area, which includes the areas on thefunction block 2 and the random logic rows 6 in the substrate 1, andwhich is arranged in a relatively higher wiring layer which is a lowerthan the clock signal wiring layer.

[0163] (6) Next, the global wiring module 505 reads the circuitinformation stored in the arrangement data memory domain 702, arranginga global signal wiring (S15). Global signal wiring arrangement beginswith the design of a global signal wiring route including at least thearrangement of orthogonal signal wiring typically arranged in either theX direction or the Y direction, arrangement of oblique signal wiring 4,and arrangement of buffering cells 3 (S16). As shown in FIG. 15, tobegin with, in the route of the global signal wirings, a function block2 with minimum signal loss is extracted by the block extraction module506 (S160). It is then determined whether or not a function block 2 withminimum signal loss exists (S161). If a function block 2 with minimumsignal loss does not exist, this global signal wiring routing designconcludes (S162). If a function block 2 with minimum signal loss exists,an arbitrary function block 2 existing near the function block 2 withminimum signal loss is extracted by the block extraction module 506(S163). The signal loss due to this function block 2 is greater than theminimum signal loss. If a function block 2 does not exist, a functionblock 2 with minimum signal loss is once again extracted (S1160). If afunction block 2 exists, the increased amount of signal loss due toarranging orthogonal signal wirings around this function block 2, orarranging oblique signal wirings passing over the function block 2 iscalculated by the evaluation module 507, and then added to thearrangement data memory domain 702 (S165). The evaluation module 507then reads from the design rule memory domain 602 the design rule forglobal signal wiring length, and when a buffering cell 3 is notarranged, determines whether or not the orthogonal signal wirings or theoblique signal wirings exceed the signal wiring length limitation(S166). If the signal wiring length exceeds the limitation, a functionblock 2 with minimum signal loss is once again extracted (S160). If thesignal wiring length does not exceed the limitation, the evaluationmodule 507 reads the design rule for signal rising/falling times fromthe design rule memory domain 602, and determines whether or not thesignal rising/falling times on the orthogonal signal wirings or theoblique signal wirings satisfy the design rule, namely whether or not atiming error occurs (S167). If the design rule is satisfied and a timingerror does not occur, the signal wiring route is decided, and thisglobal signal wiring routing design is concluded (S168). If the designrule is not satisfied and a timing error occurs, the buffering cellmodule 508 determines whether or not a buffering cell 3 can be arranged(S169). If the buffering cell 3 can be arranged, the arrangementposition of the buffering cell 3 for the signal wiring route beingdesigned is stored as a final point in the arrangement data memorydomain 702, and this global signal wiring routing design is reset at thesame time (S170). A single function block 2 is then extracted again(S163), and the same processing is repeatedly executed until a singlefunction block 2 can no longer be extracted. Meanwhile, if the bufferingcell 3 cannot be arranged, orthogonal signal wirings or oblique signalwirings are added to the current signal wiring route being designed andstored in the arrangement data memory domain 702 (S171). A singlefunction block 2 is then extracted again (S163), and the same processingis repeatedly executed. Based on the layout information for thebuffering cell 3 stored in the arrangement data memory domain 702, asshown in FIG. 14, the buffering cell 3 is additionally arranged alongthe global signal wiring route by the global wiring module 505 (S17).The global wiring module 505 designates a route for the global signalwiring including oblique signal wiring created based on the globalsignal wiring design (S18). The final route for this global signalwiring is decided (S19), and the global signal wiring is arranged.

[0164] (7) Electrical characteristics such as a timing error of thearranged global signal wiring are inspected by the inspection module 509(S20).

[0165] (8) If there are no defects as a result of the inspection,arrangement information for function blocks 2, random logic rows 6,clock signal wiring, power supply wiring, or global signal wiring arestored in the mask data memory domain 703 (S21).

[0166] (9) Based on the information created by the CAD system describedabove and stored in the mask data memory domain 703, semiconductorintegrated circuit 10 photo masks (reticles) are made.

[0167] (10) Using the photo masks, the semiconductor integrated circuit10 according to the first embodiment can be completed upon an actualsubstrate 1 by executing various fabrication processes such asphotolithography, etching and film deposition.

[0168] With the fabrication method of the semiconductor integratedcircuit 10 according to the first embodiment described above, since theglobal signal wiring that pass obliquely over the function block 2, andthe buffering cells 3 may be easily configured utilizing the CAD system,the time necessary for development of the semiconductor integratedcircuit 10 to product completion may be shortened.

[0169] Second Embodiment

[0170] A second embodiment of the present invention is one fordescribing an example that comprises a buffering cell 3 in a functionblock 2 and a global signal wiring 4 to pass obliquely over the functionblock 2 inside of the semiconductor integrated circuit 10 according tothe first embodiment.

[0171] As shown in FIG. 17, the semiconductor integrated circuit 10according to the second embodiment comprises a function block 2 upon asubstrate 1, a plurality of buffering cells 3(3 ₁₁-3 ₃₅) arranged in thefunction block 2 regularly inside at an appointed interval, and theglobal signal wiring 4 at least one part of which extends in thedirection oblique to the side of the function block 2 and is connectedbetween adjacent buffering cells 3.

[0172] The buffering cell 3 is arranged in the function block 2beforehand, and it is used appropriately when it is necessary for theglobal signal wiring 4 to pass. In FIG. 17, a broken line is added forconvenience to explain intelligibly an arrangement layout of thebuffering cell 3, but there is not a broken line on the function block 2of the semiconductor integrated circuit 10 of the real product. On amonitor screen of a CAD system, the broken line as grid can be displayedin order to do a design easily. In the second embodiment, the bufferingcell 3 is arranged at an interval by an X direction and a Y direction.In other words, the buffering cell 3 is arranged at a crossing(coordinates) of the broken line arranged at intervals of each in an Xdirection and a Y direction, or in each corner part of a squaresectioned in the broken line.

[0173] Furthermore, the buffering cell 3 according to the secondembodiment comprises the first buffering cell 3A and the secondbuffering cell 3B whose drive ability differs from each other, as oneset. Here, the first buffering cell 3A comprises the buffering cell 3having the output inverter circuit 302 of one-step structure shown inFIG. 7A, for example. The second buffering cell 3B comprises thebuffering cell 3 having output the inverter circuit 302 of two-stepstructure shown in FIG. 8A, for example. In other words, the seconddrive ability of the buffering cell 3B is stronger than the firstbuffering cell 3A.

[0174] In addition, the first buffering cell 3A may comprise thebuffering cell 3 shown in FIG. 8A or FIG. 9A, the second buffering cell3B may comprise the buffering cell 3 shown in FIG. 9A or FIG. 10.Furthermore, in the first buffering cell 3A and the second bufferingcell 3B, the number of steps of output inverter circuit 302 are made thesame, and by means of changing a gate width of IGFET Q of the invertercircuit 302, a drive ability may be adjusted.

[0175] As shown in FIG. 17, the global signal wiring 4 passes thebuffering cell 3 ₁₁, 3 ₂₂, 3 ₃₃, and 3₃₅ respectively, and connects ainput terminal S3 arranged by the second side (appearances) 2 b of thefunction block 2 and the output terminal S4 arranged on the fourth side(a lower side) 2 d of the function block 2. In other words, the globalsignal wiring 4 extends from the input terminal S3 to the lower side (Ydirection), connecting to the buffering cell 3 ₁₁ at first. The firstbuffering cell 3A is used for this buffering cell 3 ₁₁ because it doesnot need a strong drive ability so that a distance from the nextbuffering cell 3 ₂₂ can be comparatively short. And, the global signalwiring 4 extends from the buffering cell 3 ₁₁ to the lower right side asa signal wiring which is inclined by an angle of 45 degrees relative tothe second side 2 b, connecting to the buffering cell 3 ₂₂. The firstbuffering cell 3A is used for this buffering cell 3 ₂₂ because it doesnot need a strong drive ability so that a distance from the nextbuffering cell 3 ₃₃ can be comparatively short. Similarly, the globalsignal wiring 4 extends from buffering cell 3 ₂₂ to the lower right sideas a signal wiring which is inclined by an angle of 45 degrees relativeto the second side 2 b, connecting to the buffering cell 3 ₃₃. Thesecond buffering cell 3B is used for this buffering cell 3 ₃₃ because itneeds a strong drive ability so that a distance from the next bufferingcell 3 ₃₅ is comparatively long. Furthermore, the global signal wiring 4extends from the buffering cell 3 ₃₃ to the lower side (Y direction),connecting to the buffering cell 3 ₃₅. The second buffering cell 3B isused for this buffering cell 3 ₃₅ because it needs a strong driveability to drive an outside circuit of function block 2 through theoutput side S4. And, the global signal wiring 4 extends from thebuffering cell 335 to the lower side (Y direction), connecting to theoutput terminal S4.

[0176] With the semiconductor integrated circuit 10 according to thesecond embodiment configured in this manner, the global signal wiring 4can pass over the function block 2 of a huge size more than a limit ofwiring length, by using a plurality of buffering cells 3 arranged in thefunction block 2 regularly as intermediate cells.

[0177] Furthermore, a route of the global signal wiring 4 to pass overthe function block 2 can be predicted easily by having cells 3 arrangedregularly. Therefore, by arranging the electric shield layer on a routeof the global signal wiring 4 to pass the function block 2 beforehand,an electric interference between the function block 2 and the globalsignal wiring 4 to pass over the function block 2 can be minimized.

[0178] Furthermore, by using an oblique signal wiring with more than onein connection of the buffering cells 3 in the function block 2,bypassing signal wiring in the function block 2 is reduced, and routelength of the global signal wiring 4 can be shortened.

[0179] With the semiconductor integrated circuit 10 according to thesecond embodiment, the buffering cells 3 in the function block 2 may bearranged at positions corresponding to each corner part such as in atriangle, hexagon, not only a square sectioned by the broken line whichis added in convenience. In addition, the buffering cells 3 may comprisemore than three buffering cells, and are not limited to being the firstbuffering cell 3A and the second buffering cell 3B.

[0180] Third Embodiment

[0181] A third embodiment of the present invention is described using anexample that prevents cross talk between global signal wirings passingover the function block 2 in the semiconductor integrated circuit 10according to the first embodiment.

[0182] As shown in FIG. 18, the semiconductor integrated circuit 10according to the third embodiment comprises a wave guide 410 and 411that are arranged adjacent to a signal wiring 40 a and 40 b passing overthe function block 2 obliquely, extending substantially parallel to asignal wiring 40 a and 40 b. A fixed power supply is supplied in thewave guide 410 and 411. Furthermore, the semiconductor integratedcircuit 10 according to the third embodiment comprises the wave guide411 and 412 that are arranged adjacent to the signal wiring 41 a and 41b passing over the function block 2 obliquely, extending substantiallyparallel to the signal wiring 41 a and 41 b. A fixed power supply issupplied in the wave guide 411 and 412.

[0183] The signal wiring 40 a and 40 b and the signal wiring 41 a and 41b are global signal wirings and used as a bus, for example. By arrangingthe wave guide 410 along one side of signal wiring 40 a and 40 b (bottomin a figure), and arranging wave guide 411 along another side (the upperpart in a figure), there can be a layout which arranges signal wiring 40a and 40 b between wave guide 410 and 411. Similarly, by arranging thewave guide 411 along one side of signal wiring 41 a and 41 b (bottom ina figure), and arranging the wave guide 412 along another side (theupper part in a figure), there can be a layout which arranges signalwiring 41 a and 41 b between wave guide 411 and 412.

[0184] The signal wiring 40 a and 41 a and the wave guide 410 to 412which is arranged in parallel to the signal wiring 40 a and 41 a, areset in the same wiring layer to reduce electric interference between thesignal wiring 40 a and 41 a. And it is desirable for width of the waveguide 410 to 412 not to exceed a thickness of the wave guide 410 to 412in order to keep down an occupation area to a minimum. Similarly, thesignal wiring 40 b and 41 b and the wave guide 410 to 412, arranged inparallel to the signal wiring 40 a and 41 a, are set in the same wiringlayer. The wiring layer in which the signal wiring 40 a and 41 a isarranged is basically different from the wiring layer in which thesignal wiring 40 b and 41 b is arranged.

[0185] In addition, on a database of a CAD system, the wave guide 410 to412 are built in beforehand by data of the global signal wiring. Inother words, the wave guide 410 to 412 can be designed at the same timeas designing the global signal wiring. It is not necessary to design thewave guide 410 to 412 after designing the global signal wiring. It ispractical to supply 0V that has a reference power supply V_(ss) in thewave guide 410 to 412, for example.

[0186] With the semiconductor integrated circuit 10 according to thethird embodiment configured in this manner, since the wave guide 411 isarranged between the signal wiring 40 a and 40 b and between the signalwiring 41 a and 41 b at least, occurrence of electric interference,namely cross talk, can be reduced.

[0187] Other Embodiments

[0188] As described above, the semiconductor integrated circuit 10according to the first through third embodiments comprises the functionblock 2 arranged on substrate 1 (semiconductor wafer, a semiconductorchip, etc) comprising of a silicon single crystal, and the global signalwiring passing over the function block 2. These embodiment can beapplied to the semiconductor integrated circuit (a system board, amother board, a logic board, a memory board, etc) which comprises awiring substrate in which a semiconductor integrated circuit 10considered to be the function block 2 is included and the global signalwiring passes over the wiring substrate. A printed circuit board (PCB),a ceramics substrate, a carbonization silicon substrate, a glasssubstrate or the like can be used practically for the wiring substrate.

[0189] Various modifications will become possible for those skilled inthe art after receiving the teachings of the present disclosure withoutdeparting from the scope thereof.

What is claimed is:
 1. A semiconductor integrated circuit comprising: afunction block arranged on a substrate; a first buffering cell arrangedadjacent to a first side of the function block; a second buffering cellarranged adjacent to a second side adjacent to the first side of thefunction block; and signal wiring passing over the function blockobliquely relative to the first side and the second side, connecting thefirst buffering cell and the second buffering cell.
 2. The semiconductorintegrated circuit of claim 1, further comprising: a first signal wiringextending in an X direction, which extends obliquely relative to thesignal wiring; and a second signal wiring extending in a Y direction,which is perpendicular to the first signal wiring and extends obliquelyrelative to the signal wiring.
 3. The semiconductor integrated circuitof claim 2, wherein the signal wiring is arranged in a layer higher thanthe layer in which the first signal wiring and the second signal wiringare arranged.
 4. The semiconductor integrated circuit of claim 2,wherein the signal wiring has an intersecting angle either 45 degreesand 135 degree relative to either of the first signal wiring and thesecond signal wiring.
 5. The semiconductor integrated circuit of claim1, wherein the signal wiring is a global signal wiring including one ofa data bus and an address bus, arranged substantially in the entire areaon the substrate.
 6. The semiconductor integrated circuit of claim 1,wherein the first buffering cell and the second buffering cell arearranged outside of the function block.
 7. The semiconductor integratedcircuit of claim 1, further comprising a wave guide arranged adjacent tothe signal wiring and extending substantially parallel to the signal. 8.A semiconductor integrated circuit comprising: a function block arrangedon a substrate; a plurality of signal wirings having a length shorterthan a length of a side of the function block on the substrate; aplurality of buffering cells electrically connected in series betweeneach of the signal wirings; and a signal wiring passing obliquely acrossthe corner between a first side and a second side of the function block,which connects the buffering cells arranged adjacent to the first sideand adjacent to the second side adjacent to the first side of thefunction block.
 9. A semiconductor integrated circuit comprising: afunction block arranged on a substrate; a plurality of buffering cellsarranged regularly in the function block at an appointed interval; and asignal wiring extending obliquely relative to a side of the functionblock, which is connected between adjacent buffering cells.
 10. Thesemiconductor integrated circuit of claim 9, wherein each of thebuffering cells comprises a first buffering cell and a second bufferingcell having different drive abilities respectively.
 11. Thesemiconductor integrated circuit of claim 9, wherein the signal wiringis a global signal wiring including one of a data bus and an addressbus, arranged substantially in the entire area on the substrate andpasses over the function block.
 12. A method for manufacturing asemiconductor integrated circuit comprising: arranging a function blockon a substrate; arranging a signal wiring which passes over the functionblock obliquely relative to a first side and a second side adjacent tothe first side of the function block; and arranging a first bufferingcell connected to one end of the signal wiring, adjacent to the firstside of the function block and a second buffering cell connected toanother end of the signal wiring, adjacent to the second side of thefunction block.
 13. A method for manufacturing a semiconductorintegrated circuit comprising: arranging a plurality of function blockson a substrate; extracting a first function block with minimum signalloss in the function blocks in a signal wiring route; extracting asecond function block arranged near the first function block; arranginga signal wiring which passes obliquely relative to a first side and asecond side adjacent to the first side of the second function block;determining whether a length of the signal wiring exceeds the signalwiring length limitation; determining whether signal timing satisfies adesign rule at least when the length of the signal wiring exceeds thesignal wiring length limitation; determining whether a buffering cellcan be arranged when the signal timing fails to satisfy the design rule;and arranging a first buffering cell connected to one end of the signalwiring, adjacent to the first side of the second function block and asecond buffering cell connected to another end of the signal wiring,adjacent to the second side of the second function block.